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Arun Prasath, R.
- A Low Power High Speed Design Using Clustering Based Flip Flop Merging
Authors
1 Department of Electronics and Communication Engineering, Anna University, Regional Office, Madurai, Tamilnadu, IN
Source
Programmable Device Circuits and Systems, Vol 6, No 2 (2014), Pagination:Abstract
Lower in power exploitation could be a nice challenge featured up by integrated circuit industry. the main attribute is that the clock power in circuits of VLSI. In today’s VLSI design scenario, power utilization by clocking takes up an important role particularly in style that uses deeply scaled CMOS technology. Practiced power utilization tends to be a vital constraint in trendy IC style. The beneath plan of multi bit flip flop is to reduce the inverter number by sharing among flip flop. Indulging multi bit flip flop in synchronous style is turning into a considerable technique for reducing clock power. The single bit flip flop cells uses a mutual range of inverter that possess high driving capability to drive over clock signal. Grouping of such cells to make multi bit flip flop will spare drive strength, dynamic power and space of common inverter wherever there's no compromise among the mandatory constraint among area and power. In this paper, a Hausdorff clustering algorithm is used to get nearest cluster for merging flip flops. Initially D latch is taken and distance is computed for each flip flops. Then clustering is done using the proposed algorithm. After that combination table is constructed. Finally merging is done. The multi bit technique is introduced in FIR circuit to minimize power moreover as area. In line with the experimental results, our algorithm considerably reduces clock power by 19.8% and it is found that total gate count is reduced from 176 to 132. The delay is curtailed upto 1.9ns which consequently increase the speed.Keywords
Clock Power, Hausdorff, Manhattan Distance, Merging, Multi Bit Flip Flop.
- Effect of CNTFET on 4 to 2 Compressor
Authors
1 Sathyabama University, Chennai, Tamilnadu, IN
2 Jeppiaar Institute of Technology, Kunnam, Tamilnadu, IN
Source
Digital Signal Processing, Vol 4, No 6 (2012), Pagination: 254-259Abstract
This paper enumerates the efficient design and Abstract---This paper enumerates the efficient design and analysis of a 4 to 2 compressor using Full Adder cell. The Full Adder is designed using Stanford University CNTFET model and proposed 10nm CNTFET model. There are many issues facing while integrating more number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by Considering the carbon nano tube have promising application in the field of electronics. The carbon nanotube is emerging as a viable replacement to the MOSFET. The transient and power analyses are obtained with operating voltage at 0.9V. The simulation results are presented and the analyses are compared with circuits designed using 32nm MOSFET. The comparison of results indicated that the proposed 10nm CNTFET based design is more efficient in power savings and speed.